5 #ifndef _RTE_ETH_CTRL_H_
6 #define _RTE_ETH_CTRL_H_
29 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001
30 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002
31 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004
32 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008
33 #define RTE_NTUPLE_FLAGS_PROTO 0x0010
34 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020
36 #define RTE_5TUPLE_FLAGS ( \
37 RTE_NTUPLE_FLAGS_DST_IP | \
38 RTE_NTUPLE_FLAGS_SRC_IP | \
39 RTE_NTUPLE_FLAGS_DST_PORT | \
40 RTE_NTUPLE_FLAGS_SRC_PORT | \
41 RTE_NTUPLE_FLAGS_PROTO)
43 #define RTE_2TUPLE_FLAGS ( \
44 RTE_NTUPLE_FLAGS_DST_PORT | \
45 RTE_NTUPLE_FLAGS_PROTO)
47 #define RTE_NTUPLE_TCP_FLAGS_MASK 0x3F
74 #define RTE_ETH_FDIR_MAX_FLEXLEN 16
75 #define RTE_ETH_INSET_SIZE_MAX 128
81 RTE_ETH_INPUT_SET_UNKNOWN = 0,
84 RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
85 RTE_ETH_INPUT_SET_L2_DST_MAC,
86 RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
87 RTE_ETH_INPUT_SET_L2_INNER_VLAN,
88 RTE_ETH_INPUT_SET_L2_ETHERTYPE,
91 RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
92 RTE_ETH_INPUT_SET_L3_DST_IP4,
93 RTE_ETH_INPUT_SET_L3_SRC_IP6,
94 RTE_ETH_INPUT_SET_L3_DST_IP6,
95 RTE_ETH_INPUT_SET_L3_IP4_TOS,
96 RTE_ETH_INPUT_SET_L3_IP4_PROTO,
97 RTE_ETH_INPUT_SET_L3_IP6_TC,
98 RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
99 RTE_ETH_INPUT_SET_L3_IP4_TTL,
100 RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
103 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
104 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
105 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
106 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
107 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
108 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
109 RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
112 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
113 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
114 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
115 RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
116 RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
119 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
120 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
121 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
122 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
123 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
124 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
125 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
126 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
128 RTE_ETH_INPUT_SET_DEFAULT = 65533,
129 RTE_ETH_INPUT_SET_NONE = 65534,
130 RTE_ETH_INPUT_SET_MAX = 65535,
137 RTE_ETH_INPUT_SET_OP_UNKNOWN,
140 RTE_ETH_INPUT_SET_OP_MAX
251 RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
252 RTE_FDIR_TUNNEL_TYPE_NVGRE,
253 RTE_FDIR_TUNNEL_TYPE_VXLAN,
311 RTE_ETH_FDIR_ACCEPT = 0,
313 RTE_ETH_FDIR_PASSTHRU,
377 RTE_ETH_PAYLOAD_UNKNOWN = 0,
382 RTE_ETH_PAYLOAD_MAX = 8,
432 #define UINT64_BIT (CHAR_BIT * sizeof(uint64_t))
433 #define RTE_FLOW_MASK_ARRAY_SIZE \
434 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
#define RTE_ETH_INSET_SIZE_MAX
@ RTE_ETH_FDIR_NO_REPORT_STATUS
@ RTE_ETH_FDIR_REPORT_ID_FLEX_4
@ RTE_ETH_FDIR_REPORT_FLEX_8
@ RTE_FDIR_MODE_SIGNATURE
@ RTE_FDIR_MODE_PERFECT_TUNNEL
@ RTE_FDIR_MODE_PERFECT_MAC_VLAN
@ RTE_ETH_INPUT_SET_SELECT
#define RTE_ETH_FDIR_MAX_FLEXLEN
enum rte_eth_fdir_status report_status
enum rte_eth_fdir_behavior behavior
struct rte_eth_fdir_input input
struct rte_eth_fdir_action action
struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX]
struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX]
uint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN]
uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]
uint32_t flex_payload_unit
uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE]
uint32_t max_flex_bitmask_num
uint32_t flex_bitmask_unit
struct rte_eth_fdir_flex_conf flex_conf
uint16_t flex_payload_limit
uint32_t max_flex_payload_segment_num
uint8_t mac_addr_byte_mask
struct rte_eth_ipv6_flow ipv6_mask
struct rte_eth_ipv4_flow ipv4_mask
enum rte_eth_payload_type type
uint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN]
struct rte_ether_addr mac_addr
struct rte_eth_ipv4_flow ip
struct rte_eth_ipv6_flow ip
struct rte_eth_ipv4_flow ip
struct rte_eth_ipv6_flow ip
struct rte_ether_addr mac_addr
enum rte_eth_fdir_tunnel_type tunnel_type
struct rte_eth_ipv4_flow ip
struct rte_eth_ipv6_flow ip